TFT array panel and fabricating method thereof

ABSTRACT

Disclosed is display part such as a TFT array panel comprising an aluminum layer, and a molybdenum layer formed on the aluminum layer. The thickness of the molybdenum layer may be about 10% to about 40% the thickness of the aluminum layer. As a result, a top surface of the aluminum layer may have a width about equal to a bottom surface of the molybdenum layer. Accordingly, it is an aspect of the present invention to provide a TFT array panel comprising an aluminum wiring on which aluminum protrusion is reduced or eliminated.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No.2005-0011136, filed on Feb. 7, 2005, in the Korean Intellectual PropertyOffice, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to display device such as a thin filmtransistor (TFT) array panel and a fabricating method thereof.

2. Description of the Related Art

In a liquid crystal display (LCD), an LCD panel comprises a TFT arraypanel, a color filter array panel, and liquid crystal sandwiched betweenthe TFT array panel and the color filter array panel. For reference, theLCD panel cannot emit light for itself, so that there is additionallyneeded a backlight unit. Here, the backlight unit is located behind theTFT array panel and emits light toward the TFT array panel. Further, thetransmittance of the light emitted from the backlight unit is adjusteddepending on the molecular alignment of the liquid crystal.

Consumer demand for an LCD having a wide screen, high definition and ahigh aperture ratio has been increasing. As the side of LCD displaysincreases, the length of the wiring of the LCD is increasing, while thewidth thereof is decreasing. As a result, resistance values for LCDwiring are increasing. This may result in increased RC delay, which inturn may lead to distortion of displayed images.

Metals such as chrome (Cr), molybdenum-tungsten alloy (MoW) or the like,which have relatively high resistivities (e.g., 10 μΩ/cm or more), arecommonly used for the wiring material. However, the resistivity of thesematerials may be prohibitively high for wide-screened LCDs having a sizeof 20 inch or more. Accordingly, large screen LCDs may require wiringmaterials having relatively low resistivity.

Examples of lower resistivity materials include silver (Ag), copper(Cu), aluminum (Al), etc. Among these metals, silver and copper havepoor adhesion properties with respect to the glass substrate materialsused for TFT array panels. Copper and amorphous silicon (which may beused for a semiconductor layer of a TFT) may inter-diffuse, therebydamaging the TFT and lowering the resisitivity of the copper.

Because of shortcomings of silver and copper such as those describedabove, aluminum is generally used as basic material for the wiring.Aluminum has many merits such as a low resisitivity (about 3 μΩ/cm),ease of wire formation, low-cost, etc.

However, aluminum has weak corrosion-resistance to chemicals, so that itcan be easily oxidized or short-circuited. To make up for the weakcorrosion resistance, a double layer aluminum/molybdenum structure maybe used, incorporating a molybdenum upper layer. Molybdenum may be useddue to its strong corrosion-resistance to the chemicals.

However, a hillock may be formed when forming a double layeraluminum/molybdenum structure.

SUMMARY OF THE INVENTION

Systems and techniques provided herein may allow for formation of amulti-layer structure in which hillock formation is substantiallyreduced, or eliminated.

Accordingly, it is an aspect of the present disclosure to provide a TFTarray panel comprising an aluminum wiring on which a hillock issubstantially or completely prevented from growing.

Another aspect of the present disclosure is to provide a method offabricating a TFT array panel comprising an aluminum wiring on which ahillock is substantially or completely prevented from growing.

Still another aspect of the present disclosure is to provide an LCDcomprising an aluminum wiring on which a hillock is substantially orcompletely prevented from growing.

The foregoing and/or other aspects of the present disclosure canachieved by providing a display part such as a TFT array panelcomprising an aluminum layer, and a top molybdenum layer formed on thealuminum layer and having a thickness that is about 10% to 40% of thealuminum layer thickness.

According to an embodiment of the present invention, the aluminum layerand the top molybdenum layer are in direct contact with each other.

According to an embodiment of the present invention, the top molybdenumlayer has a 20% through 27% thickness of the aluminum layer.

According to an embodiment of the present invention, the top molybdenumlayer comprises at least one selected from a group consisting oftungsten (W), zirconium (Zr), tantalum (Ta), niobium (Nb), and nitrogen(N).

According to an embodiment of the present invention, the TFT array panelfurther comprises a bottom molybdenum layer formed on a bottom of thealuminum layer.

The foregoing and/or other aspects of the present disclosure canachieved by providing a device such as a TFT array panel comprising agate wiring and a data wiring, wherein at least one of the gate and datawirings comprising an aluminum layer and a top molybdenum layer having athickness about 10% to 40% of the thickness of the aluminum layer. Thealuminum layer and the molybdenum layer may be formed in sequence.

The foregoing and/or other aspects of the present disclosure canachieved by providing a method of fabricating a display part such as aTFT array panel. The method may comprise depositing an aluminum layer onan insulating substrate, depositing a top molybdenum layer on thealuminum layer having a 10% through 40% thickness of the aluminum layer,and forming a wiring by patterning the aluminum layer and the topmolybdenum layer.

According to the embodiment of the present invention, the method furthercomprises forming an insulating layer, a semiconductor layer and anohmic contact layer in sequence on the wiring by a plasma enhancedchemical vapor deposition (PECVD) method.

In general, in another aspect, a display part may comprise a substrateand a wiring on the substrate. The wiring may comprise an aluminum layerand a molybdenum layer adjacent the aluminum layer. The aluminum layerand the molybdenum layer may each extend along a first direction, andeach comprise a top surface, a bottom surface, a first lateral sidesurface having a first angle with respect to the bottom surface of thealuminum layer, and a second lateral side surface having a second anglewith respect to the bottom surface of the aluminum layer. A width of thebottom surface of the molybdenum layer perpendicular to the firstdirection may be substantially the same as a width of the top surface ofthe aluminum layer perpendicular to the first direction. Further, firstangle of the aluminum layer is substantially the same as the first angleof the molybdenum layer, and may be different than ninety degrees.

In general, in one aspect, the display part may comprise a liquidcrystal display part. In another aspect, the display part may comprisean organic light emitting diode display part.

The aluminum layer may have a first thickness, and the molybdenum layermay have a thickness between about 10% and about 40% of the. firstthickness. The relative thickness of the molybdenum layer to thealuminum layer may be selected to substantially eliminate aluminumhillock formation.

The foregoing and/or other aspects of the present disclosure canachieved by providing a display part such as a liquid crystal displaycomprising a first substrate comprising a gate wiring and a data wiring,at least one of which comprises an aluminum layer and a top molybdenumlayer having a 10% through 40% thickness of the aluminum layer, whichare formed in sequence, a second substrate facing the first substrate;and a liquid crystal layer placed between the first substrate and thesecond substrate.

In wet etching, two points are important for forming the shape of amulti-layered wiring. One is the etching rate of a single metal layer,and the other is the standard reduction potential of each metal layer.

The single metal layer etch rate of a molybdenum layer is twice that ofan aluminum layer, for an etchant such as phosphoric acid, nitric acid,acetic acid, which are exemplary etchants for wet etching.

However, in a case of a double layer structure comprising a loweraluminum layer and an upper molybdenum layer, the etching rate of themolybdenum layer becomes slower on the interface of the double layerstructure because the metal layers have different standard reductionpotentials. When adhered two metal layers are wet etched, the metallayer (anode) having relatively low standard reduction potential giveselectrons to the metal layer (cathode) having relatively high standardreduction potential. Therefore, the etch rate of the cathode metal layerof the double layer structure is decreased in comparison to the singlemetal layer etch rate, due to an effect referred to as the galvaniceffect.

Aluminum has a standard reduction potential of −1.76V, and molybdenumhas a standard reduction potential of −0.2V. In the case of amolybdenum(Mo)/aluminum(Al) double layer structure, the aluminum layer,having relatively low standard reduction potential, gives electrons tothe molybdenum layer. Therefore, the molybdenum layer receives theelectrons and has a decreased etching rate as compared with the singlemetal layer.

Meanwhile, the cause of hillock formation on a wiring is as follows.

On the way of fabricating the TFT array panel, an insulating layer, asemiconductor layer, etc. are deposited using plasma enhanced chemicalvapor deposition (PECVD) after forming an aluminum wiring. The PECVD isperformed at a high temperature of about 300° C., and thus compressivestress is applied to aluminum. At this time, the aluminum moves alongits surface, particularly, along a grain boundary and grows to lateralside or upper side of the aluminum wiring through the insulating layer,which is called the hillock.

In the case of the molybdenum(Mo)/aluminum(Al) double layer structure,it is difficult to form the wiring having a taper shape because of thegalvanic effect and the hillock. According to an embodiment of thepresent invention, the thickness ratio of the molybdenum layer to thealuminum layer is adjusted, thereby forming themolybdenum(Mo)/aluminum(Al) double layer structure having a preferredshape.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or other aspects and advantages of the present inventionwill become apparent and more readily appreciated from the followingdescription of the embodiments, taken in conjunction with the accompanydrawings of which:

FIGS. 1A through 1C are cross sectional views showing a wiring with atop molybdenum layer having a first thickness;

FIGS. 2A through 2C are cross sectional views showing a wiring with atop molybdenum layer having a second thickness;

FIGS. 3A through 3C are cross sectional views showing a wiring with atop molybdenum layer having a third thickness;

FIG. 4 shows change in an etching rate of molybdenum and aluminumaccording to a thickness ratio of the top molybdenum layer to analuminum layer;

FIGS. 5A and 5B are optical microscope photographs of an experimentalexample 1 based on <Table 1>;

FIGS. 6A and 6B are optical microscope photographs of an experimentalexample 2 based on <Table 1>;

FIGS. 7A and 7B are optical microscope photographs of an experimentalexample 3 based on <Table 1>;

FIG. 8 is an optical microscope photograph of an experimental example 4based on <Table 1>;

FIG. 9 is an optical microscope photograph of an experimental example 5based on <Table 1>;

FIGS. 10A and 10B are optical microscope photographs of an experimentalexample 6 based on <Table 1>;

FIG. 11 is a plan view of a TFT array panel according to a firstembodiment of the present invention;

FIG. 12 is a cross sectional view of the TFT array panel, taken alongline XII-XII of FIG. 11;

FIGS. 13 through 16 are cross sectional views illustrating a process offabricating the TFT array panel according to the first embodiment of thepresent invention;

FIG. 17 is a plan view of a TFT array panel according to a secondembodiment of the present invention;

FIG. 18 is a cross sectional view of the TFT array panel, taken alongline XVIII-XVIII of FIG. 17;

FIG. 19 is a cross sectional view of the TFT array panel, taken alongline XIX-XIX of FIG. 17; and

FIGS. 20 a through 27 b are cross sectional views illustrating a processof fabricating the TFT array panel according to the second embodiment ofthe present invention.

DETAILED DESCRIPTION

Reference will now be made in detail to the embodiments of the presentinvention, examples of which are illustrated in the accompanyingdrawings, wherein like reference numerals refer to like elementsthroughout.

FIGS. 1A through 1C are cross sectional views showing a wiring structurewith a top molybdenum layer having a first thickness, according to anembodiment of the present invention.

As shown in FIG. 1A, an aluminum layer 2 and a top molybdenum layer 3are deposited on an insulating substrate 1 in sequence. A photoresistlayer 9 is formed and patterned on the top molybdenum layer 3. Wetetching is performed to form a wiring corresponding to the shape of thephotoresist layer 9. For example, an etchant etches the portions of bothaluminum layer 2 and top molybdenum layer 3 that are not covered withthe-photoresist layer 9. Here, the thickness d1 of the aluminum layer 2is relatively larger than the thickness d2 of the top molybdenum layer3. The aluminum layer 2 has a relatively low standard reductionpotential function, and functions as an anode supplying electrons to thetop molybdenum layer 3, which has a relatively high standard reductionpotential.

The top molybdenum layer 3 receives the electrons from the aluminumlayer 2 and its etch rate is thus decreased by the galvanic effect.Since the thickness d1 of the aluminum layer 2 is relatively larger thanthe thickness d2 of the top molybdenum layer 3, the top molybdenum layer3 receives a relatively large number of electrons per unit mass,resulting in a substantial decrease in the etching rate. As a result,the aluminum layer 2 is etched to a relatively greater degree, and astructure shaped as shown in FIG. 1B may be formed. The top molybdenum 3is formed with an overhang A extending over the aluminum layer 2.

Referring to FIG. 1C, an insulating layer 4 made of silicon nitride orother suitable insulator, a semiconductor layer 5 made of amorphoussilicon or the like, an ohmic contact layer 6 made of n+ hydrogenatedamorphous silicon highly doped with n-type impurities are layered insequence as a triple layer on the wiring structure shown in FIG. 1B.Here, the triple layer is typically deposited by plasma enhancedchemical vapor deposition (PECVD).

At this time, a high temperature of 300° C. or more may be applied tothe wiring. As a result of the heating process, compressive stress isapplied to the aluminum layer 2, so that a hillock structure comprisinga side hillock 7 and a top hillock 8 is created (where the side and tophillocks are referred to collectively as hillock 7, 8). If its thicknessis sufficient, the top molybdenum layer 3 may be used for capping thehillock 7, 8 created in the aluminum layer 2. Referring to FIG. 1C, thethickness d1 of the top molybdenum layer 3 is too small to cap thehillock 7, 8, so that the hillock 7,8 penetrates the top molybdenumlayer 3. Hillock 7,8 may cause the wiring to be short-circuited, therebylowering the reliability of the wiring.

Further, referring to FIG. 1C, the top molybdenum layer 3 has theoverhang A, so that the triple layer adjacent to the overhang A isformed having a large layering angle. As a result, the triple layer maybe broken, which is referred to as a step open. The step open may causea short-circuit between the wirings.

FIGS. 2A through 2C are cross sectional views showing a wiring with atop molybdenum layer having a second thickness. Here, the secondthickness d3 of the top molybdenum layer 3 is relatively larger than thefirst thickness d2 of the top molybdenum layer 3 shown in FIG. 1A.

As shown in FIG. 2A, electrons from aluminum-layer 2 are transferred tothe top molybdenum layer 3. The thickness d3 of the top molybdenum layer3 is relatively large, so that the number of electrons transferred tothe top molybdenum layer 3 per unit mass is less than that in theconfiguration of FIG. 1A. Therefore, the etch rate of the top molybdenumlayer 3 is less affected by the galvanic effect, and is similar to theetch rate of a single metal layer. As a result, the top molybdenum layer3 is etched more than the aluminum layer 2, so that the wiring structureshown in FIG. 2B is formed. Referring to FIG. 2B, the aluminum layer 2has a portion B that is not capped with the top molybdenum layer 3.

Referring to FIG. 2C, a triple layer is deposited in sequence on thewiring shown in FIG. 2B. Since the layering angle of the triple layer isdecreased, the possibility of the step open arising also decreases.However, a protrusion such as side hillock 7 may grow in portion B ofthe aluminum layer 2, which is not capped with the top molybdenum layer3. Further, portion B of the aluminum layer 2 reflects external light,thereby causing a spotted image to be displayed on a screen.

FIGS. 3A through 3C are cross sectional views showing a wiring with atop molybdenum layer having a third thickness. Here, the third thicknessd4 of the top molybdenum layer 3 is between the first thickness d2 andthe second thickness d3.

As shown in FIG. 3A, electrons of the aluminum layer 2 are transferredto the top molybdenum layer 3. The thickness d4 of the top molybdenumlayer 3 is properly adjusted so as to offset the galvanic effect bydifference of the etching rate between the respective metal layers,thereby allowing the aluminum layer 2 and the top molybdenum layer 3 tohave similar etch rates. When the etch rate of the aluminum layer 2 issimilar to that of the top molybdenum layer 3, the wiring is formed withthe structure shown in FIG. 3B. Here, the aluminum layer 2 and the topmolybdenum layer 3 have a taper shape.

Referring to FIG. 3C, a triple layer is deposited in sequence on thewiring shown in FIG. 3B. At this time, the layering angle of the triplelayer is relatively small, so the possibility of the step open arisingis decreased. Further, the aluminum layer 2 is capped with the topmolybdenum layer 3, thereby preventing the hillock from growing.

As described above, the thickness ratio of the aluminum layer 2 to thetop molybdenum layer 3 is selected so that a taper is formed andprotrusions of aluminum (hillocks) are substantially prevented. One wayto determine the thickness ratio is to adjust the ratio so that the sizeof protrusions decreases. As the hillock is prevented, the wiring has ataper shape.

As shown in FIG. 4, the etch rates of molybdenum and aluminum aresubstantially equalized using a predetermined thickness ratio of themolybdenum layer to the aluminum layer. As the thickness ratio of themolybdenum layer to the aluminum layer increasingly differs from thepredetermined thickness ratio, the difference between the etch rate ofmolybdenum and aluminum increases.

For example, as the thickness of the molybdenum layer decreases, theetch rate of aluminum exceeds that of molybdenum, because molybdenum issubstantially affected by the galvanic effect. On the other hand, as thethickness of the molybdenum layer 3 increases, the etch rate ofmolybdenum exceeds that of aluminum, since the contribution to the etchrate due to the galvanic effect is substantially reduced.

Referring to FIG. 4, it is possible to determine a sufficient thicknessratio of the molybdenum layer to the aluminum layer, in order tosubstantially equalize the etch rates of aluminum and molybdenum.

EXPERIMENTAL EXAMPLE

To find a thickness ratio of the molybdenum layer to the aluminum layerat which the etch rates of the aluminum and molybdenum layers aresubstantially equalized (and hillock protrusion is substantiallyprevented), the following experiments may be performed.

The aluminum layer and the molybdenum layer are deposited in sequence onan insulating substrate using a sputtering method. For this example, thealuminum layer has a constant thickness of 3,000 Å, while the molybdenumlayer has a variable thickness ranging from 200 Å through 1,500 Å.

Thereafter, the aluminum layer and the molybdenum layer are patternedusing a wet etching method, and then a silicon nitride layer, anamorphous silicon layer, and an hydrogenated amorphous silicon layer aredeposited thereon in sequence as a triple layer using a PECVD process ata temperature of about 320° C. For this example, the silicon nitridelayer has a thickness of about 4,500 Å, the amophous silicon layer has athickness of about 2,000 Å, and the n+ hydrogenated amorphous siliconlayer has a thickness of about 500 Å.

After the triple layer is deposited, the wiring is inspected using anoptical microscope, to determine whether a top and/or side hillock hasbeen formed.

Experimental conditions and existence of the hillocks are shown in<Table 1>, and FIGS. 5A through 10B are optical microscope photographsof the experimental examples. TABLE 1 Thickness ratio of ThicknessThickness molybdenum of of layer to Experimental aluminum molybdenumaluminum Top Side examples layer (Å) layer (Å) layer (%) hillock hillock1 3,000 200 6.7 ⊚ ⊚ 2 3,000 300 10 ◯ Δ 3 3,000 600 20 ◯ X 4 3,000 800 27X Δ 5 3,000 1,200 40 X Δ 6 3,000 1,500 50 X ⊚⊚: many,◯: some,Δ: a little,X: none

Referring to FIGS. 5A and 5B, many top and side hillocks are shown. Inexperimental example 1, the thickness ratio of the molybdenum layer tothe aluminum layer are relatively small (about 6.67%), so that thehillocks are likely to penetrate the molybdenum layer.

In experimental example 2, the molybdenum layer and the aluminum layerhave a thickness ratio of 10%, so that the hillocks (particularly theside hillocks) are remarkably decreased. In experimental example 3, themolybdenum layer and the aluminum layer have a thickness ratio of 20%,so that the hillocks are remarkably decreased. Specifically, inexperimental example 3, the molybdenum layer has a sufficient thicknessto prevent the side hillock from growing.

In experimental example 4, the molybdenum layer and the aluminum layerhave a thickness ratio of 27%. In experimental example 4, there is notop hillock; however, a small side hillock is shown. Further, inexperimental examples 5 and 6, the molybdenum layer and the aluminumlayer have thickness ratios of 40% and 50%, respectively. In theseexamples, there is no top hillock but the side hillocks are increased.Particularly, the side hillocks are substantially increased inexperimental example 6.

As the thickness ratio increases, the top hillock is prevented fromprotruding through the molybdenum layer (since the molybdenum layer isrelatively thickner). However, as the thickness ratio of the molybdenumlayer to the aluminum layer increases, the etching rate of themolybdenum layer increases. Therefore, the aluminum layer has a portionthat is not capped with the molybdenum layer, and thus the side hillockcan grow in this portion.

Based on the foregoing experimental examples, the thickness ratio of themolybdenum layer to the aluminum layer preferably ranges from 10% to40%, to reduce the protrusion of hillocks (note that herein, rangesinclude the endpoints). Particularly, the thickness ratio of themolybdenum layer to the aluminum layer preferably ranges from 20% to 27%so as to decrease both the top hillocks and the side hillocks.

Exemplary embodiments of a TFT array panel and a fabricating methodthereof will be described.

FIG. 11 is a plan view of a TFT array panel according to a firstembodiment of the present invention; FIG. 12 is a cross sectional viewof the TFT array panel, taken along line XII-XII of FIG. 11; and FIGS.13 through 16 are cross sectional views illustrating a process offabricating the TFT array panel according to the first embodiment of thepresent invention.

Gate wiring 22, 24 and 26 is formed on an insulating substrate 10. Here,each gate wiring 22, 24, 26 incorporates a multi-layer structure (e.g.,dual layer), comprising an aluminum layer 221, 241, 261 and a topmolybdenum layer 222, 242, 262. The thickness of top molybdenum layer222, 242, 262 is between about 10% and about 40% of the thickness of thecorresponding aluminum layer 221, 241, 261.

Gate wiring 22, 26 includes a gate line 22 formed in a horizontaldirection, and a gate electrode 26 included in a thin film transistorand connected to the gate line 22, wherein the width of one end portion24 of gate line 22 is enlarged to be connected with an external circuit.

Further, a gate insulating layer 30 may be formed on the insulatingsubstrate 10. Gate insulating layer 30 may comprise, for example,silicon nitride (SiNx) or the like, and may cover the gate wiring 22,24, 26.

A semiconductor layer 40 comprising amorphous silicon or the like may beformed on the gate insulating layer 30 of gate electrodes 26. Ohmiccontact layers 55 and 56 comprising (for example) n+ hydrogenatedamorphous silicon highly doped with n-type impurities may be formed onsemiconductor layer 40.

Data wiring 65, 66, 68 may be formed on the ohmic contact layers 55, 56and the gate insulating layer 30. Data wiring 65, 66, 68 may also have adouble layer structure comprising an aluminum layer 651, 661, 681 and atop molybdenum layer 652, 662, 682. Here, the thickness of the topmolybdenum layer 652, 662, 682 may be about 10% through 40% of thethickness of the aluminum layer 651, 661, 681.

The data line 62, illustrated in FIG. 11, is not shown in FIGS. 12-16but may have the same double layer structure as the data wiring 65, 66,68.

The data wiring 62, 65, 66, 68 comprises the data line 62 formed in avertical direction and intersecting the gate line 22 to define a pixel,a source electrode 65 branched from the data line 62 and extended overthe ohmic contact layer 55, and a drain electrode 66 separated from thesource electrode 65 and formed over the ohmic contact layer 56. Drainelectrode 66 may be positioned opposite the source electrode 65 acrossthe gate electrode 26. Additionally, the width of one end 68 of the dataline 62 may be enlarged to be connected to the external circuit.

Further, a passivation layer 70 may be formed on the data wiring 62, 65,66, 68 and a portion of the semiconductor layer 40 not covered with thedata wiring 62, 65, 66, 68. The passivation layer may comprise a SiNxlayer, an a-Si:C:O layer, a-Si:O:F layer (low dielectric CVD layer), anacryl-based organic insulating layer, or other layer. An a-Si:C:O layerand/or a a-Si:O:F layer may be formed using a plasma-enhanced chemicalvapor deposition (PECVD) method, and may have a low dielectric constantof 4 or below (e.g., may have a dielectric constant in the range from 2to 4). Because of their relatively low dielectric constants, evenrelatively thin layers of a-Si:C:O or a-Si:O:F layer may have relativelylow parasitic capacitances. Further, the a-Si:C:O and a-Si:O:F layersexhibit excellent step coverage and contact properties with respect toother layers. Also, a-Si:C:O and a-Si:O:F layers are inorganic CVDlayers, and therefore have good heat-resistance compared to organicdielectric layers. Additionally, a deposition rate and an etching rateof a-Si:C:O layers and a-Si:O:F layers are four through ten times higherthan those of SiNx, so that using an a-Si:C:O layer and/or an a-Si:O:Flayer rather than SiNx may reduce process time.

The passivation layer 70 has a contact hole 76 through which the drainelectrode 66 is exposed, a contact hole 78 through which an end portion68 of the data line is exposed, and a contact hole 74 through which anend portion 24 of the gate line and the gate insulating layer 30 areexposed.

A pixel electrode 82 is formed on the passivation layer 70. Pixelelectrode 82 may be electrically connected to the drain electrode 66through the contact hole 76, and located on a pixel region. Contactsubsidiary parts 86, 88 may be formed on passivation layer 70. Contactsubsidiary parts 86, 88 may be connected to the end portion 24 of thegate line and the end portion 68 of the data line through the contacthole 74 and 78, respectively. Pixel electrode 82 and contact subsidiaryparts 86, 88 may comprise a transparent conductive material such as ITO(indium tin oxide), IZO (indium zinc oxide), or other transparentconductive material. Drain electrode 82 may contact the pixel electrode82 through the molybdenum layer 662.

Referring to FIGS. 11 and 12, the pixel electrode 82 is overlapped withthe gate line 22, thereby forming a storage capacitor. If thecapacitance of the storage capacitor is not sufficient, a storagecapacitor line assembly may be provided at the same level as the gatewiring 22, 24, 26.

Further, the pixel electrode 82 may be overlapped with the data lines62, to increase or maximize an aperture ratio. In such a configuration,the parasitic capacitance between the pixel electrode 82 and the dataline 62 can generally be ignored, as long as the passivation layer 70 isa low dielectric constant layer (e.g., a low dielectric constant CVDlayer as described above).

A method of fabricating the TFT array panel, according to someembodiments, is as follows. As shown in FIG. 13, a multi-layer gateconductor layer is formed on the insulating substrate 10. The gateconductor layer may have the double layer structure comprising thealuminum layer 221, 241, 261 and the top molybdenum layer 222, 242, 262.Thereafter, the gate metal layer is patterned by photolithography usinga mask, to form the gate wiring 22, 24, 26. The gate wiring 22, 24, 26includes the gate lines 22 and the gate electrodes 26, and extends inthe horizontal direction (where directions are referred to as horizontaland vertical for illustrative purposes).

Referring to FIG. 14, gate insulating layer 30 (for example, siliconnitride), semiconductor layer 40 (for example, amorphous silicon), and adoped amorphous silicon layer 50 are sequentially deposited onto theinsulating substrate 10. Semiconductor layer 40 and doped amorphoussilicon layer 50 are patterned by photolithography using a mask. As aresult, semiconductor layer 40 and ohmic contact layer 50 form anisland-like structure on gate insulating layer 30 over gate electrode26.

Referring to FIG. 15, a data metal layer having the double layerstructure comprising the aluminum layer 651, 661, 681 and the topmolybdenum layer 652, 662, 682 is deposited and patterned byphotolithography using a mask, to form the data wiring including thedata line 621. The data wiring comprises the data line 62 intersectingthe gate line 22, the source electrode 65 connected to the data line 62and extending over the gate electrode 26, and the drain electrode 66isolated from the source electrode 65 and opposite to the sourceelectrode 65 across the gate electrode 26.

Subsequently, the doped amorphous silicon layer 50 is etched to expose aportion of the semiconductor layer 40 between separate opposite dopedamorphous silicon layers 55 and 56. Additionally, the structure may beplaced in an oxygen plasma environment to stabilize the surface of theexposed semiconductor layer 40.

Then, referring to FIG. 16, passivation layer 70 may be formed. Forexample, passivation layer 70 may be formed by growing a silicon nitridelayer, an a-Si:C:O layer, or an a-Si:C:F layer using a CVD method, or bycoating the structure using an organic insulating material.

The passivation layer 70 and the gate insulating layer 30 may then bepatterned by the photolithography to form the contact holes 74, 76, 78exposing the end portion 24 of the gate line, a portion of the drainelectrode 66, and the end portion 68, respectively.

Finally, referring to FIGS. 11 and 12, the ITO layer or the IZO layer isdeposited and etched using photolithography techniques, thereby formingthe pixel electrode 82 electrically connected to the drain electrode 66through the contact hole 76 and forming the contact subsidiary parts 86,88 respectively connected to the end portion 24 of the gate line and theend portion 68 of the data line through the contact holes 74, 78.Preferably, the structure is pre-heated in a nitrogen gas atmospherebefore depositing the transparent conductor (e.g., ITO layer or IZO)layer.

The above-described first embodiment employs five masks in fabricatingthe TFT array panel, but the following second embodiment employs fourmasks.

FIG. 17 is a plan view of a TFT array panel according to a secondembodiment of the present invention; FIG. 18 is a cross sectional viewof the TFT array panel, taken along line XVIII-XVIII of FIG. 17; FIG. 19is a cross sectional view of the TFT array panel, taken along lineXIX-XIX of FIG. 17; and FIGS. 20A through 27B are sectional viewsshowing a process of fabricating the TFT array panel according to someembodiments of the present invention.

Like the first embodiment, gate wiring 22, 24, 26 having a double layerstructure comprising a aluminum layer 221, 241, 261 and a top molybdenumlayer 222, 242, 262 is formed on insulating substrate 10. The topmolybdenum layer 222, 242, 262 may have a thickness that is 10% to 40%thickness of the aluminum layer 221, 241, 261.

Further, a storage electrode line 28 parallel to gate line 22 may beformed on the insulating substrate. Storage electrode line 28 has thesame double layer structure as the gate wiring 22, 24, 26. The storageelectrode line 28 is overlapped with a storage capacitor conductivepattern 64 connected to the pixel electrode 82 (to be described later),and forms a storage capacitor enhancing the electrical potential storagecapacitance of a pixel. If the storage capacitance resulting from theoverlap of the pixel electrode 82 with the gate line 22 is sufficient,the storage electrode line 28 can be omitted. In general, voltageapplied to the storage electrode line 28 is equal to voltage applied toa common electrode of a top substrate.

Gate insulating layer 30, which may be a silicon nitride SiNx layer orthe like, may be formed on the gate wiring 22, 24, 26 and the storageelectrode line 28, thereby covering the gate wiring 22, 24, 26 and thestorage electrode line 28.

Semiconductor patterns 42 and 48, which may comprise a semiconductormaterial such as hydrogenated amorphous silicon or the like, may beformed on the gate insulating layer 30. An ohmic contact pattern or anintermediate layer pattern 55, 56, 58 may be formed on the semiconductorpatterns 42 and 48. Pattern 55, 56, 58 may be made of amorphous siliconor the like, and may be highly doped with n-type impurities such asphosphorous (P).

On the ohmic contact layer 55, 56 and 58 is formed a data wiring 62, 64,65, 66, 68 having a double layer structure comprising the aluminum layer621, 641, 651, 661, 681 and the top molybdenum layer 622, 642, 652, 662,682 may be formed on ohmic contact layer 55, 56, 58. The top molybdenumlayer 622, 642, 652, 662, 682 may have a thickness that is about 10% to40% thickness of the aluminum layer 621, 641, 651, 661, 681. The datawiring comprises a data line portion 62, 68, 65 extending in a verticaldirection. The data line portion 62, 68, 65 comprise a data line 62having an end portion 68 to receive an external video signal, and asource electrode 65 of the thin film transistor branched from the dataline 62. Further, the data wiring comprises a drain electrode 66 of thethin film transistor separated from the data line portion 62, 68, 65 andopposite to the source electrode 65 with respect to the gate electrode26 or TFT channel portions C. Also, the data wiring comprises a storagecapacitor conductive pattern 64 disposed on the storage electrode line28. If the storage electrode line 28 is not provided, the storagecapacitor conductive pattern 64 can be omitted.

The ohmic contact patterns 55, 56, 58 are used for lowering the contactresistance between the underlying semiconductor patterns 42, 48 and theoverlying data wiring 62, 64, 65, 66, 68, and have the same shape as thedata wiring 62, 64, 65, 66, 68. That is, the ohmic contact pattern 55located under the data line part 62, 68, 65 has the same shape as thedata line part 62, 68, 65; the ohmic contact pattern 56 located underthe drain electrode 66 has the same shape as the drain electrode 66; andthe ohmic contact pattern 58 located under the storage capacitorconductive pattern 64 has the same shape as the storage capacitorconductive pattern 64.

The semiconductor patterns 42, 48 have a similar shape as the datawiring 62, 64, 65, 66, 68 and the ohmic contact patterns 55, 56, 58,except for the TFT channel portions C. In more detail, the storagecapacitor semiconductor pattern 48, the storage capacitor conductivepattern 64, and the storage capacitor ohmic contact pattern 58 havesimilar shapes. The TFT semiconductor pattern 42 differs in shape fromthe data wiring and the other portions of the ohmic contact patterns.That is, at the TFT channel portion C, particularly, the sourceelectrode 65 and the drain electrode 66 of the data line part 62, 68, 65are separated from each other, and the data line intermediate layerpattern 55 and the drain electrode ohmic contact pattern 56 areseparated from each other. However, the TFT semiconductor pattern 42continuously extends at the TFT channel portion C without separation,thereby forming the channel of the thin film transistor.

Passivation layer 70, which may comprise silicon nitride, a-Si:C:O layeror a-Si:O:F layer (low dielectric layer) deposited by the PECVD method,organic insulating layer, or other passivation layer, is formed on thedata wiring 62, 64, 65, 66, 68. The passivation layer 70 has contactholes 76, 78, 72 through which the drain electrodes 66, the end portion68 of the data line, and the storage capacitor conductive pattern 64 areexposed, respectively. Further, the passivation layer 70 has a contacthole 74. The contact hole 74 penetrates the gate insulating layer 30 andexposes the end portion 24 of the gate line 22.

The pixel electrode 82 to receive a video signal from the thin filmtransistors and generate an electric field together with an upperelectrode (not shown) is formed on the passivation layer 70. The pixelelectrode 82 is made of a transparent conductive material such as ITO,IZO or the like. The pixel electrode 82 is physically and electricallyconnected to the drain electrode 66 via the contact hole 76, therebyreceiving the video signal. Here, the pixel electrode 82 is overlappedwith the neighboring gate line 22 and the neighboring data line 62 toenhance the aperture ratio. Alternatively, the pixel electrode 82 may benot overlapped with the neighboring gate line 22 and the neighboringdata line 62.

The pixel electrode 82 may further be electrically connected to thestorage capacitor conductive pattern 64 through the contact hole 72 andmay transmit the video signal to the storage capacitor conductivepattern 64. Meanwhile, contact subsidiary parts 86, 88 are formed overthe end portion 24 of the gate line and the end portion 68 of the dataline, and are connected to both the end portion 24 of the gate line andthe end portion 68 of the data line through the contact holes 74, 78,respectively. The contact subsidiary parts 86, 88 enhance adhesion ofthe end portions 24, 68 to external circuits and protect the endportions 24, 68, respectively. The contact subsidiary parts 86, 88 aremade of a transparent conductive material, such as ITO, IZO, and/orother appropriate material.

A method of fabricating the TFT array panel according to the secondembodiment of the present invention is as follows. As shown in FIGS. 20Athrough 20B, the aluminum layer 221, 241, 261, 281 and the topmolybdenum layer 222, 242, 262, 282 are deposited and patterned by thephotolithography (as described above with respect to the firstembodiment), thereby forming the gate wiring comprising the gate line 22and the gate electrode 26, and the storage capacitor electrode 28. Atthis point in the process, the width of one end portion 24 of the gateline 22 is enlarged to be connected with an external circuit.

Thereafter, referring to FIGS. 21A and 21B, the gate insulating layer 30having a thickness of about 1500 Å through about 5000 Å, thesemiconductor layer 40 having a thickness of about 500 Å through about2000 Å, and the intermediate layer 50 having a thickness of about 300 Åto about 600 Å are sequentially deposited by the CVD method. Theconductive layer 60 having a double layer structure comprising analuminum layer 601 and a molybdenum layer 602 is deposited to form thedata wiring. Then, a photoresist film 110 having a thickness of about 1μm to about 2 μm is coated onto the conductive layer 60.

Referring to FIGS. 22A and 22B, the photoresist film 110 is exposed tolight through a mask, and developed to thereby form a photoresistpattern 112, 114. A first photoresist pattern portion 114 positioned atthe TFT channel portion C between the source and drain electrodes 65, 66is established to have a thickness smaller than that of a secondphotoresist pattern portion 112 positioned at a data wiring portion E inwhich the data wiring 62, 64, 65, 66, 68 will be formed. On the otherhand, the photoresist pattern portion 110 positioned at the otherportion D is removed. At this time, the thickness ratio of the firstphotoresist pattern portion 114 positioned at the TFT channel portion Cto the second photoresist pattern portion 112 remaining at the datawiring portion E should be controlled depending upon the processingconditions in the subsequent etching process. For example, for a firstset of processing conditions, the thickness of the first photoresistpattern portion 114 may be formed to be about ½ or less of that of thesecond photoresist pattern portion 112. Preferably, the thickness of thefirst photoresist pattern portion 114 can be formed to be about 4000 Åor less.

According to an embodiment of the present invention, various methods canbe used to differentiate the thickness of the photoresist film 110. Themethods may employ a slit pattern, a lattice pattern or asemitransparent film to control the light transmissivity in the portionC.

For a process using a slit pattern or a lattice pattern, it ispreferable that the width of the slit or lattice be smaller than thelight decomposition capability of a light exposure apparatus. For aprocess using semitransparent film, the semitransparent film can have atleast two thin films different in transmissivity or thickness to adjustthe amount of light coupled to photoresist in an exposure process.

When the photoresist film is exposed to light through the mask, polymersof the photoresist film 110 directly exposed to light are substantiallyfully decomposed (i.e., one or more bonds of the polymer molecule arebroken so that a subsequent development process will remove thematerial). Further, the polymers of the photoresist film correspondingto the slit pattern or the semitransparent film of the mask aredecomposed to a lesser degree, so that not all of the photoresist willbe removed in the subsequent development process. However, the polymersof the photoresist film blocked from the mask are not decomposed.

When the photoresist film 110 is developed after exposing to the light,the portions where the polymers are not decomposed remain. The portionswhere substantially all of the photoresist is decomposed aresubstantially removed. The portions where some of the photoresist isdecomposed and some is not remain, with a thickness that is less thanthe thickness of the regions that were not exposed to light. Thethickness of the remaining photoresist depends on the extent of theexposure to the light. The light exposing time should be not so longthat all the molecules of the photoresist film are prevented from beingdecomposed.

Alternatively, the first photoresist pattern portion 114 having arelatively thin thickness can be formed using a photoresist film capableof reflow. The photoresist film is exposed to light through a usual maskwith a light transmission portion and a light interception portion.Then, the light-exposed photoresist film is developed, and reflows suchthat the film portion is partially flown to the non-film area, therebyforming a thin photoresist pattern 114.

Thereafter, the first photoresist pattern portion 114 and its underlyinglayers, (e.g., the conductive layer 60, the intermediate layer 50, andthe semiconductor layer 40) are etched. At this time, the data wiringand its underlying layers remain at the data wiring portion E, and onlythe semiconductor layer 40 remains at the TFT channel portion C.Further, the conductive layer 60, the intermediate layer 50, and thesemiconductor layer 40 are all removed at the other portion D, therebyexposing the underlying gate insulating layer 30.

First, referring to FIGS. 23A and 23B, the conductive layer 60 exposedat the other portion D is removed, thereby exposing the underlyingintermediate layer 50. According to an embodiment of the presentinvention, either a dry etching method or a wet etching method can beused for etching the conductive layer 60. Both etching methods arepreferably performed so that the photoresist pattern portions 112, 114are hardly etched while the conductive layer 60 is etched (i.e., theetch process is selective of conductive layer 60 with respect tophotoresist pattern portions 112, 114). However, in the case of the dryetching method, it is difficult to find etch parameters that do not etchthe photoresist pattern portions 112, 114. Therefore, the dry etchingmethod may be performed under conditions in which both the conductivelayer 60 and the photoresist pattern portions 112, 114 are etched. Forthe dry etching method, the first photoresist pattern portion 114 isformed to be thicker than the first photoresist pattern portion 114 fora wet etching method, in order to prevent the underlying conductivelayer 60 from being exposed.

Consequently, as shown in FIGS. 23A and 23B, the conductive layer at thechannel area C and the data wiring area E is patterned. That is, thesource/drain conductive pattern 67 and the storage capacitor conductivepattern 64 remain, whereas the conductive layer 60 placed at the otherportion D is substantially removed, thereby exposing the underlyingintermediate layer 50. At this time, the remaining conductive patterns67, 64 have a similar shape as the data wiring 62, 64, 65, 66, 68,except that source and drain electrodes 65 and 66 are not yet separatedfrom each other and connected to each other. Furthermore, when the dryetching method is performed, the photoresist pattern portions 112 and114 are also removed (to some degree).

Referring to FIGS. 24A and 24B, the intermediate layer 50 exposed at theother portion D and the underlying semiconductor layer 40, together withthe first photoresist pattern portion 114, are simultaneously removed bythe dry etching method. At this time, the dry etching method isperformed under the conditions that the photoresist pattern portions 112and 114, the intermediate layer 50, and the semiconductor layer 40(where, the semiconductor layer and the intermediate layer has no etchselectivity) are simultaneously etched, whereas the gate insulatinglayer 30 is not etched. Particularly, the dry etching method ispreferably performed under the conditions that the etching rates withrespect to the photoresist patterns 112 and 114 and the semiconductorlayer 40 are approximately similar to each other.

For example, a gas mixture of SF₆ and HCl, or SF₆ and O₂ is used to etchthe photoresist pattern 112 (or 114) and the semiconductor layer 40 bysubstantially the same amount. When the etching rates of the photoresistpatterns 112 and 114 and the semiconductor layer 40 are the same orsubstantially the same, the thickness of the first photoresist pattern114 is preferably the same as or less than the sum of the thicknesses ofthe semiconductor layer 40 and the intermediate layer 50.

Consequently, as shown in FIGS. 24A and 24B, the first photoresistpattern portion 114 at the channel portion C is removed, and thesource/drain conductive pattern 67 is exposed. The intermediate layer 50and the semiconductor layer 40 at the other portion D area are removed,and the underlying gate insulating layer 30 is exposed. Meanwhile, thesecond photoresist pattern portion 112 at the data wiring portion E isalso etched, so that the thickness thereof is reduced. Further, in thisprocess, the semiconductor patterns 42 and 48 are formed. Referencenumerals 57 and 58 indicate the intermediate pattern under thesource/drain conductive pattern 67 and the intermediate pattern underthe storage capacitor conductive pattern 64, respectively.

Then, photoresist residue on the source/drain conductive pattern 67 atthe channel portion C is removed using an ashing process.

Thereafter, referring to FIGS. 25A and 25B, the source/drain conductivepattern 67 and the source/drain intermediate layer pattern 57 at thechannel portion C area are etched and removed. According to anembodiment of the present invention, the dry etching method is appliedto both the source/drain conductive pattern 67 and the source/drainintermediate layer pattern 57. Alternatively, the wet etching method canbe applied to the source/drain conductive pattern 67, and the dryetching method can be applied to the source/drain intermediate layerpattern 57.

In the former case, it is preferable that the etch selectivity of thesource/drain conductive pattern 67 to the source/drain intermediatelayer pattern 57 is high. If the etching selectivity is not high, it isdifficult to find the end point of the etching process and to controlthe thickness of the semiconductor pattern 42 remaining at the channelportion C. In the latter case (that is, when the wet etching method andthe dry etching method are alternated), lateral sides of thesource/drain conductive pattern 67 are etched by the wet etching method,but lateral sides of the source/drain intermediate layer pattern 57 arenot substantially etched by dry etching, so that a cascade structure isformed. A gas mixture of CF₄ and HCl, or CF₄ and O₂ can be preferablyused for etching the intermediate layer pattern 57 and the semiconductorpattern 42. When the mixture gas of CF₄ and O₂ is used, thesemiconductor pattern 42 may have a substantially uniform thickness.

At this time, as shown in FIG. 25B, the semiconductor pattern 42 can bepartially removed (i.e., its thickness is reduced), and the secondphotoresist pattern portions 112 may be etched so that their thicknessdecreases by a predetermined amount. The etching method should beperformed under the conditions that the gate insulating layer 30 is notsubstantially etched. It is preferable that the thickness of the secondphotoresist pattern 112 is large enough to prevent the underlying datawiring 62, 64, 65, 66, 68 from being exposed when etched.

As a result, the source electrodes 65 and the drain electrodes 66 areseparated from each other, thereby completing the data wiring 62, 64,65, 66, 68 and the underlying ohmic contact patterns 55, 56, 58.

Finally, the second photoresist pattern portion 112 remaining at thedata wiring area E is removed. Alternatively, the second photoresistpattern portion 112 can be removed before removing the underlyingintermediate layer pattern 57 after removing the source/drain conductivepattern 67 at the channel portion C.

As described above, the wet etching method and the dry etching methodcan be alternately used, or only the dry etching method can be used. Inthe latter case, the process is simple but it is relatively difficult tofind the proper etching conditions. Contrary, in the former case, it isrelatively easy to find the proper etching conditions, but the processis complicated.

As shown in FIGS. 26A to 26B, the passivation layer 70 is formed bygrowing silicon nitride, a-Si:C:O layer or a-Si:O:F layer through theCVD method, or applying an organic insulating film.

Referring to FIGS. 27A and 27B, the passivation layer 70, together withthe gate insulating layer 30, is etched to form contact holes 76, 74,78, 72 through which the drain electrodes 66, the end portion 24 of thegate line, the end portion 68 of the data line, and the storagecapacitor conductive pattern 64 are exposed, respectively.

Finally, referring to FIGS. 18 and 19, the ITO layer or the IZO layerhaving a thickness of about 400 Å to about 500 Å is deposited and etchedto form the pixel electrode 82 connected to the drain electrode 66 andthe storage capacitor conductive pattern 64, and to form the contactsubsidiary data part 88 connected to the end portion 24 of the gate lineand the contact subsidiary gate part 86 connected to the end portion 68of the data line.

Meanwhile, nitrogen gas can be used in a pre-heating process performedbefore depositing the ITO or IZO layer. The nitrogen gas prevents theoxidation of the metal layer 24, 64, 66, 68 exposed through the contactholes 72, 74, 76, 78 respectively.

According to the second embodiment of the present invention, the datawiring 62, 64, 65, 66, 68, the underlying ohmic contact patterns 55, 56,58 and the semiconductor patterns 42 and 48 are etched using one mask,and at the same time, the source and drain electrodes 65 and 66 areseparated from each other, thereby simplifying the fabricating process.

The foregoing embodiments may vary. For example, the top molybdenumlayer may include one of tungsten (W), zirconium (Zr), tantalum (Ta),niobium (Nb), and nitrogen (N). Additionally, a bottom molybdenum layermay be formed on a bottom of the aluminum layer, thereby forming awiring having a triple layer structure.

Alternatively, the TFT array panel according to an embodiment of thepresent invention can be used in not only a TFT LCD but also an organiclight emitting diode (OLED) apparatus (or the like).

An OLED uses an organic material that emits light in response to areceived electric signal (e.g., a data signal indicative of displaydata). An OLED may have a layered structure comprising an anode layer(pixel electrode), a hole injecting layer, a hole transporting layer, anemission layer, an electron transporting layer, an electron injectionlayer, and a cathode layer (counter electrode) According to anembodiment of the present invention, the drain electrode of the TFTarray panel is electrically connected to the anode layer, therebytransmitting the data signal. On the other hand, the drain electrode ofthe TFT substrate is electrically connected to the cathode layer.

As described above, embodiments of the present invention provides a TFTarray panel comprising an aluminum wiring having an improved structurefor reducing or eliminating hillock formation, and a fabricating methodthereof.

Although a few embodiments of the present invention have been shown anddescribed, it will be appreciated by those skilled in the art thatchanges may be made in these embodiments without departing from theprinciples and spirit of the invention, the scope of which is defined inthe appended claims and their equivalents.

1. A TFT array panel comprising: an aluminum layer having a thickness;and a top molybdenum layer formed on the aluminum layer, the topmolybdenum thickness having a thickness in the range from about 10% toabout 40% the thickness of the aluminum layer.
 2. The TFT array panelaccording to claim 1, wherein the aluminum layer and the top molybdenumlayer are in direct contact with each other.
 3. The TFT array panelaccording to claim 1, wherein the thickness of the top molybdenum layeris in the range of about 20% to 27% of the thickness of the aluminumlayer.
 4. The TFT array panel according to claim 1, wherein the topmolybdenum layer comprises at least one selected from a group consistingof tungsten (W), zirconium (Zr), tantalum (Ta), niobium (Nb), andnitrogen (N).
 5. The TFT array panel according to claim 1, furthercomprising a bottom molybdenum layer formed adjacent a bottom of thealuminum layer.
 6. A TFT array panel comprising: a gate wiring; and adata wiring, wherein at least one of the gate and data wiring comprisesan aluminum layer having an aluminum layer thickness and a molybdenumlayer having a molybdenum thickness about 10% to 40% of the aluminumlayer thickness, and wherein the aluminum layer and the molybdenum layerare formed in sequence.
 7. A method of fabricating a TFT array panel,comprising: depositing an aluminum layer having a first thickness on asubstrate; depositing a molybdenum layer on the aluminum layer, themolybdenum layer having a second thicknes about 10% to about 40% thefirst thickness; and forming a wiring by patterning the aluminum layerand the molybdenum layer.
 8. The method according to claim 7, furthercomprising forming an insulating layer, a semiconductor layer and anohmic contact layer in sequence on the wiring.
 9. The method accordingto claim 8, wherein forming an insulting layer, a semiconductor layer,and an ohmic contact layer in sequence comprises forming at least one ofthe insulating layer, the semiconductor layer, and the ohmic contactlayer using a plasma-enhanced chemical vapor deposition process.
 10. Aliquid crystal display comprising: a first substrate comprising a gatewiring and a data wiring, at least one of the gate wiring and the datawiring comprising an aluminum layer having a first thickness and amolybdenum layer having a second thickness in the range from about 10%to about 40% of the first thickness, the aluminum layer and themolybdenum layer formed in sequence; a second substrate facing the firstsubstrate; and a liquid crystal layer placed between the first substrateand the second substrate.
 11. The liquid crystal display of claim 10,wherein the aluminum layer and the molybdenum layer each extend along afirst direction, and each comprise a top surface, a bottom surface, afirst lateral side surface having a first angle with respect to thebottom surface of the aluminum layer, and a second lateral side surfacehaving a second angle with respect to the bottom surface of the aluminumlayer, and wherein a width of the bottom surface of the molybdenum layerperpendicular to the first direction is substantially the same as awidth of the top surface of the aluminum layer perpendicular to thefirst direction.
 12. The liquid crystal display of claim 10, wherein thefirst angle of the aluminum layer is substantially the same as the firstangle of the molybdenum layer.
 13. A display part, comprising: asubstrate; a wiring on the substrate, the wiring configured to transmitone or more electrical signals in the display part, wherein the wiringcomprises: an aluminum layer; a molybdenum layer adjacent the aluminumlayer, wherein the aluminum layer and the molybdenum layer each extendalong a first direction, and each comprise a top surface, a bottomsurface, a first lateral side surface having a first angle with respectto the bottom surface of the aluminum layer, and a second lateral sidesurface having a second angle with respect to the bottom surface of thealuminum layer, and wherein a width of the bottom surface of themolybdenum layer perpendicular to the first direction is substantiallythe same as a width of the top surface of the aluminum layerperpendicular to the first direction.
 14. The part of claim 13, whereinthe first angle of the aluminum layer is substantially the same as thefirst angle of the molybdenum layer.
 15. The part of claim 14, whereinthe first angle is different than ninety degrees.
 16. The part of claim13, wherein the display part comprises at least one of a liquid crystaldisplay part and an organic light emitting diode display part.
 17. Thepart of claim 13, further comprising a bottom layer extending along thefirst direction, the bottom layer having a top surface adjacent thebottom surface of the aluminum layer.
 18. The part of claim 13, whereinthe molybdenum layer further comprises at least one of tungsten (W),zirconium (Zr), tantalum (Ta), niobium (Nb), and nitrogen (N).
 19. Thepart of claim 13, wherein the aluminum layer has a first thickness, andwherein the molybdenum layer has a thickness between about 10% and about40% of the first thickness.
 20. The part of claim 19, wherein thethickness of the molybdenum layer is selected to substantially eliminatealuminum hillock formation.